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[Other resource] crc16_ccitt

Description: crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a verilog module of byte paralle crc. CRC16_D8_m_tb.v is the testbench file of above module.
Platform: | Size: 3242 | Author: 樊文杰 | Hits:

[Other] CLOCK_co-design_of_C_and_Verilog

Description: A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
Platform: | Size: 37796 | Author: Annbb | Hits:

[Other] Find_medium_value_co-design_of_C_and_Verilog

Description: A code writing by Verilog which can find medium value. With a C file to see the simulation results. A co-design example of C and Verilog.
Platform: | Size: 11025 | Author: Annbb | Hits:

[Other Embeded program] Traffic_control

Description: 一个用verilog语言编写的用来模拟交通信号灯的程序，包含测试文件-A use of Verilog language used to simulate the procedures for traffic signals, including the test file
Platform: | Size: 1024 | Author: zhangyanbo | Hits:

[SCM] clock

Description: 一个用verilog编写的数字时钟，最后在8段数码管上显示出来，对于初学verilog的有一定的帮助，是一个工程文件-Verilog prepared using a digital clock, the last paragraph in 8 out digital tube display, for the novice Verilog have some help, is a project file
Platform: | Size: 603136 | Author: wphyl | Hits:

[Other] Find_medium_value_co-design_of_C_and_Verilog

Description: A code writing by Verilog which can find medium value. With a C file to see the simulation results. A co-design example of C and Verilog.
Platform: | Size: 11264 | Author: Annbb | Hits:

[SCM] upload_code

Description: 每个代码见压缩包内文件名，分别为使用单片机控制AD9627的代码，已在硬件电路实现；基于FPGA的DDR SDRAM控制源代码，将文件夹内文件加入同一工程即可；以及三份FPGA内部学习资料。 C代码开发环境为KeilC，verilog代码开发环境为Quartus。 -See each code within the compressed package file name, respectively, for the use of the AD9627 single-chip control of code, has been in the hardware circuit FPGA-based DDR SDRAM control source code, will be adding a document folder to the same project and three FPGA internal learning materials. C code development environment for KeilC, verilog code development environment for the Quartus.
Platform: | Size: 1746944 | Author: 姜琰俊 | Hits:

[VHDL-FPGA-Verilog] Bin2Grey

Description: 一个用Verilog语言实现的二进制码到BCD码的一种转换方法的实现。包含工程文件和实现文档。-Verilog language implementation with a binary code to BCD code conversion method as a realization. And the achievement of the document contains the project file.
Platform: | Size: 82944 | Author: 文闯 | Hits:

[VHDL-FPGA-Verilog] ClockRun

Description: 一个用Verilog语言实现的简单的时钟模拟。包含工程文件和实现文档。-Verilog language implementation with a simple analog clock. And the achievement of the document contains the project file.
Platform: | Size: 91136 | Author: 文闯 | Hits:

[VHDL-FPGA-Verilog] counters

Description: 一个用Verilog语言实现的变计数器。包含工程文件和实现文档。-Verilog language implementation with a variable counter. And the achievement of the document contains the project file.
Platform: | Size: 98304 | Author: 文闯 | Hits:

[VHDL-FPGA-Verilog] BIN_CV_MEN

Description: 可將2進位檔案 轉換成適合verilog應用的文字檔-2 into digital files can be converted to a text file for verilog applications
Platform: | Size: 1024 | Author: Henry | Hits:

[Embeded-SCM Develop] Advanced_Digital_Design_with_the_Verilog_HDL-M.D.C

Description: 此文件为学习更进一步的学习verilog语言提供了一个教学，是国外的一套教材，很好-This file is learning to learn verilog language further provides a teaching, is a set of foreign materials, good
Platform: | Size: 36900864 | Author: 陈小飞 | Hits:

[Other] daima

Description: Verilog下寄存器的开发代码，下载到Spartan3的引脚代码以及波形仿真文件-Under the development of Verilog register code, download Spartan3 a pin code and waveform simulation file
Platform: | Size: 2048 | Author: sherry | Hits:

[VHDL-FPGA-Verilog] SEQ_DETECTOR

Description: 这是一个四位串行数据检测器，一共有三种模式可以选择：递增（检测连续四位递增序列），递减（检测连续四位递减序列）和不变（检测连续四位不变序列）。整个设计采用同步时钟，异步复位，用米利状态机，并配置好了仿真环境和仿真文件。(This is a four bit sequence detector, including three modes that can be selected: increment mode (detecting four consistency increment data), decrement mode (detecting four consistency decrement data) and steadiness mode (detecting four consistency same data). The whole design adopts synchronous clock, asynchronous reset, and uses Mealy state machine. The whole file concludes the simulation environment and testbench.)
Platform: | Size: 1855488 | Author: LLawliet | Hits:

[VHDL-FPGA-Verilog] 07_uart_test

Description: uart通信协议的Verilog编码实现，以及完整的测试文件。(UART communication protocol Verilog encoding implementation, as well as a complete test file.)
Platform: | Size: 359424 | Author: 声声不洗 | Hits:

[VHDL-FPGA-Verilog] project_zyg

Description: 利用HC——SR04的超声波模块与EGO1板子外加一个EMAX电机形成一个测距报警器 上传文件为vivado程序(Using the HC - SR04 ultrasonic module and the EGO1 board plus a EMAX motor to form a range finder to upload the file as the vivado program)
Platform: | Size: 2009088 | Author: nbnm | Hits:

[VHDL-FPGA-Verilog] lcd5110_耗费资源少

Description: Quartus II 项目，可驱动LCD5110液晶显示屏。(This zip file contains a quartus ii project, which can driven the LED screen LCD5110.)
Platform: | Size: 4725760 | Author: 蝠蝙 | Hits:

[Com Port] d974d4330bf7

Description: 这是一个非常完整的qpsk调制解调用fpga实现的工程，在工程中已经能够正常使用，使用的quartus ii 开发，使用Verilog语言，文件中还包含了各种滤波器的系数文件，还有matlab仿真文件，整个工程包含从串并变换，相位映射，到成型滤波，中通滤波，cic滤波，调制，再到解调过成的下变频，匹配滤波，载波提取，位定时，判决，整个完整的过程(This is a very complete QPSK modulation and demodulation using FPGA implementation of the project, the project has been able to properly use the Quartus II development, the use of Verilog language, the file also contains the files of various filter coefficients, and MATLAB simulation files, including the entire project from the string and transform, phase mapping, molding in filtering, filtering, CIC filtering, modulation, and demodulation frequency, a matched filter, carrier extraction, timing, judgment, the whole course)
Platform: | Size: 13488128 | Author: maerzaizai | Hits:

[SCM] verilog

Description: this is a file about a microprocessor en multiples sections
Platform: | Size: 23552 | Author: teck | Hits:

[VHDL-FPGA-Verilog] i2c_verilog

Description: 主要包含i2c的master、slave模块，和一个简单的仿真sim文件(It mainly includes I2C master, slave module, and a simple SIM file)
Platform: | Size: 5120 | Author: 时光乄星河 | Hits:
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